;
; Copyright (c) Microsoft Corporation.  All rights reserved.
;
;
; Use of this sample source code is subject to the terms of the Microsoft
; license agreement under which you licensed this sample source code. If
; you did not accept the terms of the license agreement, you are not
; authorized to use this sample source code. For the terms of the license,
; please see the license agreement between you and Microsoft or, if applicable,
; see the LICENSE.RTF on your install media or the root of your tools installation.
; THE SAMPLE SOURCE CODE IS PROVIDED "AS IS", WITH NO WARRANTIES OR INDEMNITIES.
;
;
; (C) Copyright 2006 Marvell International Ltd.
; All Rights Reserved
;
;++
;
; Module Name:
;
;   monahans_base_regs.inc
;
; Abstract:
;
;    Intel Monahans CPU register addresses and register field definitions.
;
; Environment:
;
; Revision History:
;
;--
;
; Copyright ?2002-2003 Intel Corp.
;

    IF  !:DEF: _monahans_base_regs_inc_
_monahans_base_regs_inc_    EQU 1


; ////////////////////////////////////////////////////
; /* DEVICE BASE ADDRESSES GROUPED BY FUNCTIONALITY */
; ////////////////////////////////////////////////////

;
; Internal Memory - Storage (768 KB)
;
MONAHANS_BASE_REG_PA_IMSTORAGE                   EQU 0x5C000000

;
; Internal Memory - Control (12 B)
;
MONAHANS_BASE_REG_PA_IMCONTROL                   EQU 0x58000000

;
; Camera Peripheral
;
MONAHANS_BASE_REG_PA_CAMERA                      EQU 0x50000000

;
; USB 1.0 Host
;
MONAHANS_BASE_REG_PA_USBH                        EQU 0x4C000000

;
; USB 2.0 Host
;
MONAHANS_BASE_REG_PA_USB2H			 EQU 0x54100000
   
;
;  Dynamic MEMC (DMC)
;
MONAHANS_BASE_REG_PA_DMEMC                       EQU 0x48100000

;
;  Static MEMC (SMC)
;
MONAHANS_BASE_REG_PA_SMEMC                       EQU 0x4A000000

;
;  Data Flash Controller (DFC)
;
MONAHANS_BASE_REG_PA_DFC                         EQU 0x43100000

;
; LCDC
;
MONAHANS_BASE_REG_PA_LCD                         EQU 0x44000000

;
; 2D Graphics
;
MONAHANS_BASE_REG_PA_2D				 EQU 0x54000000
     
;
; Peripheral registers base - DMAC, UART[3:1/SIR], I2S/C, AC97, USBC, FIR, 
; RTC, OST, PWM, INTC, GPIO, PWRMAN/RESETC, SSP[3:1], MMC, CLKMAN, BB, KEYPAD, 
; USIM, MEMSTICK
;
MONAHANS_BASE_REG_PA_PERIPH                      EQU 0x40000000

;
; Mini LCD
;
MONAHANS_BASE_REG_PA_MLCD			 EQU 0x46000000

;
; Px 1 and 2 Arbiters
;
MONAHANS_BASE_REG_PA_PXARB			 EQU 0x4600FE00

;
; ASSP PMU.  Can be mapped to core PMU events 0x80-0x87
;
MONAHANS_BASE_REG_PA_ASSPPMU			 EQU 0x4600FF00

;
; Caddo Module
;
MONAHANS_BASE_REG_PA_CADDO			 EQU 0x43000000

;
; PCMCIA Slots 0,1
;
MONAHANS_BASE_REG_PA_PCMCIA_IO                	EQU 0x20000000
MONAHANS_BASE_REG_PA_PCMCIA_ATTR              	EQU 0x28000000
MONAHANS_BASE_REG_PA_PCMCIA_CMN               	EQU 0x2C000000


; /////////////////////////////////////////////////////////////////////////////////////////
; /* Peripheral register offsets */
; /////////////////////////////////////////////////////////////////////////////////////////


;//
;//  mmr-perifs
;//
DMAC_OFFSET                     EQU     0x0             ; DMA CONTROLLER
FFUART_OFFSET                   EQU     0x00100000      ; Full-Feature UART
BTUART_OFFSET                   EQU     0x00200000      ; BlueTooth UART
I2C_OFFSET                      EQU     0x00300000      ; I2C
AC97_OFFSET                     EQU     0x00500000      ; AC97
UDC_OFFSET                      EQU     0x00600000      ; UDC (usb client)
SIRUART_OFFSET                  EQU     0x00700000      ; SIR UART
RTC_OFFSET                      EQU     0x00900000      ; real time clock
OST_OFFSET                      EQU     0x00A00000      ; OS Timer
PWM0_2_OFFSET                   EQU     0x00B00000      ; PWM 0 (pulse-width mod)
PWM1_3_OFFSET                   EQU     0x00C00000      ; PWM 1 (pulse-width mod)
INTC_OFFSET                     EQU     0x00D00000      ; Interrupt controller
GPIO_OFFSET                     EQU     0x00E00000      ; GPIO
PWR_OFFSET                      EQU     0x00F00000      ; Power Manager and Reset Control
SSP1_OFFSET                     EQU     0x01000000      ; SSP 1
MMC_OFFSET                      EQU     0x01100000      ; MMC
CLKMGR_OFFSET                   EQU     0x01300000      ; Clock Manager
BB_OFFSET                       EQU     0x01400000      ; Baseband Interface
KEYPAD_OFFSET                   EQU     0x01500000      ; Keypad Interface
USIM_OFFSET                     EQU     0x01600000      ; USIM
SSP2_OFFSET                     EQU     0x01700000      ; SSP 2
SSP3_OFFSET                     EQU     0x01900000      ; SSP 3
SSP4_OFFSET			EQU     0x01A00000	; SSP 4
ONEWIRE_OFFSET			EQU	0x01B00000	; 1-wire
TSI_OFFSET			EQU	0x01C00000	; Touch Screen Interface/ADC
CIR_OFFSET			EQU	0x01D00000	; Consumer IR
MMC2_OFFSET			EQU	0x02000000	; MMC 2
USIM2_OFFSET			EQU	0x02100000	; USIM 2


; /////////////////////////////////////////////////////////////////////////////////////////
; /* Peripheral-specific base addresses */
; /////////////////////////////////////////////////////////////////////////////////////////

MONAHANS_BASE_REG_PA_FFUART     EQU     (MONAHANS_BASE_REG_PA_PERIPH + FFUART_OFFSET)
MONAHANS_BASE_REG_PA_BTUART     EQU     (MONAHANS_BASE_REG_PA_PERIPH + BTUART_OFFSET)
MONAHANS_BASE_REG_PA_SIRUART    EQU     (MONAHANS_BASE_REG_PA_PERIPH + SIRUART_OFFSET)
MONAHANS_BASE_REG_PA_RTC        EQU     (MONAHANS_BASE_REG_PA_PERIPH + RTC_OFFSET)
MONAHANS_BASE_REG_PA_OST        EQU     (MONAHANS_BASE_REG_PA_PERIPH + OST_OFFSET)
MONAHANS_BASE_REG_PA_INTC       EQU     (MONAHANS_BASE_REG_PA_PERIPH + INTC_OFFSET)
MONAHANS_BASE_REG_PA_GPIO       EQU     (MONAHANS_BASE_REG_PA_PERIPH + GPIO_OFFSET)
MONAHANS_BASE_REG_PA_PWR        EQU     (MONAHANS_BASE_REG_PA_PERIPH + PWR_OFFSET)
MONAHANS_BASE_REG_PA_CLKMGR     EQU     (MONAHANS_BASE_REG_PA_PERIPH + CLKMGR_OFFSET)

; /////////////////////////////////////////////////////////////////////////////////////////
; /* Peripheral-specific offsets */
; /////////////////////////////////////////////////////////////////////////////////////////

;//
;// FULL-FEATURE UART
;//
FF_THR_OFFSET                   EQU     0x0       ;DLAB = 0  WO  8bit - Transmit Holding Register
FF_RBR_OFFSET                   EQU     0x0       ;DLAB = 0  RO  8bit - Receive Buffer Register
FF_DLL_OFFSET                   EQU     0x0       ;DLAB = 1  RW  8bit - Divisor Latch Low Register
FF_IER_OFFSET                   EQU     0x4       ;DLAB = 0  RW  8bit - Interrupt Enable Register
FF_DLH_OFFSET                   EQU     0x4       ;DLAB = 1  RW  8bit - Divisor Latch High Register
FF_IIR_OFFSET                   EQU     0x8       ;DLAB = X  RO  8bit - Interrupt Identification Register
FF_FCR_OFFSET                   EQU     0x8       ;DLAB = X  WO  8bit - FIFO Control Register
FF_LCR_OFFSET                   EQU     0xC       ;DLAB = X  RW  8bit - Line Control Register
FF_MCR_OFFSET                   EQU     0x10      ;DLAB = X  RW  8bit - Modem Control Regiser
FF_LSR_OFFSET                   EQU     0x14      ;DLAB = X  RO  8bit - Line Status Register
FF_MSR_OFFSET                   EQU     0x18      ;DLAB = X  RO  8bit - Modem Status Register
FF_SPR_OFFSET                   EQU     0x1C      ;DLAB = X  RW  8bit - Scratchpad Register
FF_ISR_OFFSET                   EQU     0x20      ;DLAB = X  RW  8bit - Slow Infrared Select Register
FF_FOR_OFFSET                   EQU     0x24      ;DLAB = X  RO  FIFO Occupancy Register
FF_ABR_OFFSET                   EQU     0x28      ;DLAB = X  RW  Autobaud Control Register
FF_ACR_OFFSET                   EQU     0x2C      ;DLAB = X Autobaud Count Register
					     
;
; Slave Power Management Unit (40F0_0000 --> 40F4_003C)
; Assume offset from 0x40F0_0000
;
SPMU_ASCR_OFFSET				EQU		0x40000						     
SPMU_ARSR_OFFSET				EQU		0x40004
;; (...more...)

; defs added for startups
;
ARSR_ALL	EQU 0xF
ASCR_RDH        EQU (0x1<<31)


; ~~~~~~~~~~ BELOW ITEMS UNTOUCHED FROM BVD.  Some stuff removed ~~~~~~~~~~~~~~


RCSR_ALL                        EQU     0x1F
Mode_SVC                        EQU     0x13
Mode_USR                        EQU     0x10
NoIntsMask                      EQU     0x000000C0
IRQIntsMask                     EQU     0x7F      ; 0=enabled, 1=disabled
IrqFiqEnable                    EQU     0xFFFFFF3F

;
; FLASH constants
;
K3_128Mb_DEVCODE                EQU     0x8806
J3_128Mb_DEVCODE                EQU     0x18
L3_128Mb_DEVCODE                EQU     0x880C

;
; Reset Controller Status Register bit defines
;
RCSR_HARD_RESET                 EQU     (0x1)
RCSR_WDOG_RESET                 EQU     (0x1 << 1)
RCSR_SLEEP_RESET                EQU     (0x1 << 2)
RCSR_GPIO_RESET                 EQU     (0x1 << 3)
PSSR_VALID_MASK                 EQU     (0x3F)
PSSR_RDH                        EQU     (0x1 << 5)
PSSR_PH                         EQU     (0x1 << 4)


;
;   Bits used for the HWConfig Reg (aka PowerManager.ScratchPad)
;
HWConfig_RESET                  EQU     (0x1  :SHL:  0)
HWCONFIG_DEFAULT                EQU     (0x01155046)
HWConfig_BootromPM              EQU     (0x1  :SHL:  12)
PAGEMODE_ON                     EQU     (0x1)

;
;   Bits used for CP 15
;
CONTROL_MMU                     EQU     0x00000001

    ENDIF ; !:DEF: _bvd1regs_inc_
    
    END
